Novel dual bit split gate flash memory

ABSTRACT

The dual bit split gate flash memory of the invention comprises a plurality of memory cells wherein each memory cell comprises a select gate overlying a substrate and isolated from the substrate by a select gate oxide layer, a first and second floating gate on opposite sidewalls of the select gate and isolated from the select gate by an oxide spacer, and a control gate overlying the select gate and the first and second floating gates and isolated from the select gate and the first and second floating gates by a dielectric layer, and source and drain regions within the substrate and shared by adjacent memory cells.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates to the fabrication of integratedcircuit devices, and more particularly, to the fabrication of a dual bitflash memory having increased bit density over a single bit flashmemory, but without the disadvantages of multi-level cell technology.

[0003] (2) Description of the Prior Art

[0004] Improvements in Flash memory devices are sought continuously. Onearea of desired improvement is in bit density. One way to increase bitdensity in flash memory is to adopt a multi-level cell technology. Themulti-level cells store fractional levels of charge within a cell toprovide increased data storage capability. This means that each of thelevels requires a precisely metered number of electrons to be stored inthe floating gate and each of the levels has its own threshold voltage(Vt) margin. As a result, program operation needs to be performedcarefully and is inherently slow in comparison with conventional singlebit technology program operation. Furthermore, multi-level cell devicesgenerally much use higher operating voltages to ensure a Vt window wideenough to accommodate all levels. The associated high fields result inoxide wear-out and limit the endurance of the device. It is desired toincrease bit density without resorting to multi-level cell technology.

[0005] U.S. Pat. No. 6,462,375 to Wu et al discloses two floating gateshaving a shared select gate/control gate therebetween. U.S. Pat. Nos.6,151,248, 6,344,993 and 6,266,278 to Harari et al show floating gateson the sidewalls of a select gate. U.S. Pat. Nos. 6,133,098, 6,366,500,and 6,359,807 to Ogura et al describe two floating gates on thesidewalls of a select gate wherein a control gate separates each set ofselect gate/floating gates.

SUMMARY OF THE INVENTION

[0006] Accordingly, it is a primary object of the invention to provide amethod for fabricating a flash memory having increased bit density inthe fabrication of integrated circuits.

[0007] Another object of the invention is to provide a dual bit splitgate flash memory having two floating gates separated by a select gate,all underlying a control gate.

[0008] A further object is to provide a method of fabricating a splitgate flash memory having increased bit density.

[0009] A still further object is to provide a method of fabricating adual bit split gate flash memory.

[0010] Yet another object is to provide a method of fabricating a dualbit split gate flash memory having two floating gates separated by aselect gate, all underlying a control gate.

[0011] In accordance with the objects of the invention, a method offabricating a dual bit split gate flash memory is achieved. A selectgate oxide layer is provided on the surface of a substrate. A firstpolysilicon layer is deposited overlying the select gate oxide layer. Aa capping layer is deposited overlying the first polysilicon layer. Thecapping layer, first polysilicon layer, and select gate layer arepatterned to form a plurality of select gates. Spacers are formed onsidewalls of the select gates. A tunneling oxide layer is grown on thesubstrate exposed between the select gates. A second polysilicon layeris deposited overlying the tunneling oxide layer and the select gatesand etched back below a top surface of the select gates. An interpolydielectric layer is deposited overlying the second polysilicon layer andthe select gates. A third polysilicon layer is deposited overlying theinterpoly dielectric layer. A capping oxide layer is deposited overlyingthe third polysilicon layer. The capping oxide layer, third polysiliconlayer, and second polysilicon layer are patterned to form a plurality ofmemory cells wherein a portion of the second polysilicon layer remainson either side of each of the select gates forming first and secondfloating gates for each memory cell and wherein the third polysiliconlayer covers the select gate and the first and second floating gate ofeach memory cell and forms a control gate. Ions are implanted to formsource and drain regions within the substrate between memory cellswherein the source and drain regions are shared by adjacent memory cellsto complete fabrication of a dual-bit split gate flash memory.

[0012] Also in accordance with the objects of the invention, a dual bitsplit gate flash memory is achieved. The dual bit split gate flashmemory comprises a plurality of memory cells wherein each memory cellcomprises a select gate overlying a substrate and isolated from thesubstrate by a select gate oxide layer, a first and second floating gateon opposite sidewalls of the select gate and isolated from the selectgate by an oxide spacer, and a control gate overlying the select gateand the first and second floating gates and isolated from the selectgate and the first and second floating gates by a dielectric layer, andsource and drain regions within the substrate and shared by adjacentmemory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the accompanying drawings forming a material part of thisdescription, there is shown:

[0014]FIGS. 1-6 are a cross-sectional representations of a preferredembodiment of the process of the present invention.

[0015]FIG. 7 is a cross-sectional representation of the dual bit splitgate flash memory of the present invention.

[0016]FIG. 8 is a cross-sectional representation of the dual bit splitgate flash memory of the present invention showing programmingoperation.

[0017]FIG. 9 is a cross-sectional representation of the dual bit splitgate flash memory of the present invention showing erasing operation.

[0018]FIG. 10 is a cross-sectional representation of the dual bit splitgate flash memory of the present invention showing reading operation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The process of the present invention provides a dual bit splitgate flash memory and a method of making the same. Each memory cellpossesses two floating gates having very short channel lengths andseparated by a select gate under a single control gate. Each cell canstore electrons into the two separated floating gates independently bysource-side injection and erase them by Fowler-Nordheim tunneling. Thedata in each bit is selected by the source/drain bit line and reverseread independently.

[0020] The process of the present invention begins with a preferablydoped semiconductor substrate 10, illustrated in FIG. 1. Now a gatestack is formed. First a thin oxide layer is formed. This will be theselect gate oxide 12, formed by deposition or thermal oxidation on thesurface of the substrate to a thickness of between about 29 and 35Angstroms. Now, a first polysilicon layer 14 is deposited on the oxidelayer 12, such as by low pressure chemical vapor deposition (LPCVD), toa thickness of between about 1000 and 1200 Angstroms. Now, a cappingoxide layer 16 is formed such as by high temperature oxide (HTO) havinga thickness of between about 800 and 1000 Angstroms.

[0021] Referring now to FIG. 2, the gate stack is patterned to formselect gates 18 having gaps therebetween. Next, a second HTO depositionis performed overlying the select gates. The HTO layer isanisotropically etched to leave HTO spacers 20 on the sidewalls of theselect gates, as shown in FIG. 3. The HTO spacers 20 have a width ofbetween about 400 and 500 Angstroms. A tunneling oxide layer 22 is grownon the exposed substrate 10 between the select gates, as shown. Thetunneling oxide layer 22 has a thickness of between about 80 and 100Angstroms.

[0022] Referring now to FIG. 4, a second thick polysilicon layer isdeposited to fill the gaps between the select gates. The polysiliconlayer should have a thickness of between about 2000 and 2500 Angstroms.The second polysilicon layer is then etched back or polished back usingchemical mechanical polishing (CMP), for example, to below the surfaceof the HTO capping layer 18 on the select gates. This separates andself-aligns the polysilicon 26 along the select gates. The resultingpolysilicon layer 26 should have a thickness of between about 1300 and1600 Angstroms.

[0023] Referring now to FIG. 5, an interpoly dielectric layer 28 isformed. For example, this may be an ONO layer comprising a HTO oxidelayer, a silicon nitride layer, and a HTO oxide layer, each having athickness of between about 60 and 70 Angstroms, deposited in sequence. Athird polysilicon layer 30 is deposited on the ONO layer 28 to athickness of between about 2000 and 2400 Angstroms. A capping layer 32of tetraethoxysilane (TEOS) oxide, for example, is deposited over thethird polysilicon layer to a thickness of between about 1000 and 1300Angstroms.

[0024] The stack of second polysilicon, ONO, third polysilicon, and TEOScap is patterned aligning with the select gate pattern. The criticaldimension (CD) of the stack covers the first polysilicon CD, the spacerwidth of the two HTO spacers, and the minimum overlay tolerance. FIG. 6shows the resulting devices. The second polysilicon layer 26 remainingon the sidewalls of the HTO spacers 20 forms floating gates on eitherside of the select gate 16. The floating gates each have a thickness ofbetween about 1300 and 1600 Angstroms and a length of between about 500and 700 Angstroms, for example. The third polysilicon layer remaining 30forms a single control gate overlying the select gate and two floatinggates.

[0025] Now a spacer dielectric layer 34 is formed on the sidewalls ofthe stack pattern for isolation, as shown in FIG. 7. This dielectriclayer may comprise HTO, TEOS oxide, or a composite film such asHTO/SiN/HTO. The spacers 34 will have a width of between about 400 and500 Angstroms. The drain 36 and source 38 are implanted self-aligned tothe control gate electrodes 30. LDD regions, not shown, are formedbefore formation of the spacers 34.

[0026] This completes fabrication of the dual bit split gate flashmemory of the present invention. Each memory cell possesses two floatinggates 26. These act as two virtual transistors to increase the densityof the memory bit. Each of these floating gates can be read, erased, andprogramed independently of each other and at full power. The floatinggates have a very short channel length. For example, in 0.18 technology,the channel length is between about 0.05 and 0.07 m. The floating gates26 are separated by a select gate 16 under a single control gate 30.Drain and source regions 36 and 38, respectively, lie within thesemiconductor substrate on either side of the memory cell and are sharedwith adjacent memory cells.

Device Operation

[0027] The flash memory cell of the present invention can storeelectrons into the two separated floating gates independently bysource-side hot electron injection. Programming of the drain side bit bysource-side hot electron injection is illustrated in FIG. 8.

[0028] The TEOS capping layer has been removed and the control gateelectrode electrically connected, for example, through a polysiliconvia, not shown in this view. The voltages shown are typical values. Forexample, a select gate voltage of between about 1.5 and 2 volts isapplied, a control gate voltage of between about 9 and 12 volts isapplied, and a drain voltage of between about 5 and 7 volts is appliedfor a duration of more than about 5 microseconds per bit.

[0029] The select gate voltage is applied to the select gate 16. Thecontrol gate voltage is applied to the control gate 30 and the drainvoltage is applied to the drain 36. The source and the substrate areconnected to ground, as shown. Hot electrons are injected from thesource to the drain side and into the floating gate bit 26, as shown byarrows 41 and 43.

[0030] The flash memory cell of the present invention is erased byFowler-Nordheim tunneling of electrons from the floating gate to thedrain or source. The erasing of the drain-side bit is shown in FIG. 9.The voltages shown are typical values. For example, a negative biascontrol gate voltage of between about −5 and −7 volts is applied and apositive bias of the drain voltage of between about 5 and 7 volts isapplied for a duration of more than about 5 milliseconds per bit. Thecontrol gate voltage is applied to the control gate 30 and the drainvoltage is applied to the drain 36. The source 38 and the substrate 10are connected to ground, as shown. Tunneling of electrons 45 from thedrain-side floating gate bit 26 to the drain 36, shown by arrow 45,erases the information in the floating gate bit 26.

[0031] The data in each bit is selected by the source/drain bit line andreverse read independently. FIG. 10 illustrates the reverse readmechanism to read the drain-side bit. The channel under the unselectedbit (the source-side bit in the illustrated case) is forced intoconductive depletion. The whole channel impedance will depend on thethreshold voltage of the selected bit. Thus, the bit state of theunselected bit does not affect reading of the selected bit. The voltagesshown are typical values. For example, a control gate voltage of betweenabout 1.5 and 2 volts is applied, a select gate voltage of between about1.5 and 2 volts is applied, a source voltage of between about 1.5 and 2volts is applied, and the drain voltage is set to 0. The select gatevoltage is applied to the select gate 16. The control gate voltage isapplied to the control gate 30 and the source voltage is applied to thesource 38. A zero voltage is applied to the drain 36. The substrate isconnected to ground, as shown. The channel under the source-side bit isforced into conductive depletion. The depletion region 53 isillustrated. The inversion region 51 is the channel formed by theinversion carriers. Arrow 55 shows the electrons being swept across thedepletion region toward the source.

[0032] The process of the present invention provides a novel dual-bitsplit gate architecture wherein each memory cell holds two virtualtransistors to increase the density of the memory bit. Each of the bitscan be read, erased, and programed independently of the other and atfull power. The Vt margins of each bit are the same as that in singlebit flash memories regardless of the select gate Vt. The operation speedand endurance are superior to those in multi-level cells. The minimumcell channel length (under the two floating gates and one select gate)depends only on lithography resolution and overlay tolerance, so can beshrunken easily.

[0033] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A dual-bit split gate flash memory comprising: aplurality of memory cells wherein each memory cell comprises: a selectgate overlying a substrate and isolated from said substrate by a selectgate oxide layer; a first and second floating gate on opposite sidewallsof said select gate and isolated from said select gate by an oxidespacer; and a control gate overlying said select gate and said first andsecond floating gates and isolated from said select gate and said firstand second floating gates by a dielectric layer; and source and drainregions within said substrate and shared by adjacent said memory cells.2. The memory according to claim 1 wherein a channel length under saidselect gate and said first and second floating gates is between about0.05 and 0.07 microns in 0.18 micron technology.
 3. The memory accordingto claim 1 wherein said select gate comprises: a polysilicon layerhaving a thickness of between about 1000 and 1200 Angstroms; and adielectric capping layer having a thickness of between about 800 and1000 Angstroms.
 4. The memory according to claim 3 wherein saiddielectric capping layer comprises high temperature oxide.
 5. The memoryaccording to claim 1 wherein said select gate oxide has a thickness ofbetween about 29 and 35 Angstroms.
 6. The memory according to claim 1wherein said oxide spacer comprises high temperature oxide and has awidth of between about 400 and 500 Angstroms.
 7. The memory according toclaim 1 wherein first and second floating gates are isolated from saidsubstrate by a tunneling oxide having a thickness of between about 80and 100 Angstroms.
 8. The memory according to claim 1 wherein said firstand second floating gates have a thickness of between about 1300 and1600 Angstroms and a length of between about 500 and 700 Angstroms. 9.The memory according to claim 1 wherein said control gate comprisespolysilicon having a thickness of between about 2000 and 2400 Angstroms.10. The memory according to claim 1 wherein said dielectric layercomprises a first layer of high temperature oxide, a second layer ofsilicon nitride, and a third layer of high temperature oxide, each layerhaving a thickness of between about 60 and 70 Angstroms.
 11. A method offabricating a dual-bit split gate flash memory comprising: providing aselect gate oxide layer on the surface of a substrate; depositing afirst polysilicon layer overlying said select gate oxide layer;depositing a capping layer overlying said first polysilicon layer;patterning said capping layer, said first polysilicon layer and saidselect gate layer to form a plurality of select gates; forming spacerson sidewalls of said select gates; growing a tunneling oxide layer onsaid substrate exposed between said select gates; depositing a secondpolysilicon layer overlying said tunneling oxide layer and said selectgates and etching back said second polysilicon layer to below a topsurface of said select gates; depositing an interpoly dielectric layeroverlying said second polysilicon layer and said select gates;depositing a third polysilicon layer overlying said interpoly dielectriclayer; depositing a capping oxide layer overlying said third polysiliconlayer; patterning said capping oxide layer, said third polysiliconlayer, and said second polysilicon layer to form a plurality of memorycells wherein a portion of said second polysilicon layer remains oneither side of each of said select gates forming first and secondfloating gates for each memory cell and wherein said third polysiliconlayer covers said select gate and said first and second floating gate ofeach said memory cell and forms a control gate; and implanting ions toform source and drain regions within said substrate between said memorycells wherein said source and drain regions are shared by adjacentmemory cells to complete fabrication of said dual-bit split gate flashmemory.
 12. The method according to claim 11 wherein said select gateoxide layer has a thickness of between about 29 and 30 Angstroms. 13.The method according to claim 11 wherein said first polysilicon layerhas a thickness of between about 1000 and 1200 Angstroms.
 14. The methodaccording to claim 11 wherein said capping layer comprises hightemperature oxide having a thickness of between about 800 and 1000Angstroms.
 15. The method according to claim 11 wherein said spacerscomprise high temperature oxide and have a width of between about 400and 500 Angstroms.
 16. The method according to claim 11 whereintunneling oxide has a thickness of between about 80 and 100 Angstroms.17. The method according to claim 11 wherein said step of depositingsaid interpoly dielectric layer comprises: depositing a first hightemperature oxide layer overlying said second polysilicon layer and saidselect gates; depositing a silicon nitride layer overlying said firsthigh temperature oxide layer; and depositing a second high temperatureoxide layer overlying said silicon nitride layer wherein each of saidlayers has a thickness of between about 60 and 70 Angstroms.
 18. Themethod according to claim 11 wherein third polysilicon layer has athickness of between about 2000 and 2400 Angstroms.
 19. The methodaccording to claim 11 wherein said capping oxide layer comprises TEOSoxide having a thickness of between about 1000 and 1300 Angstroms.
 20. Amethod of programming a dual-bit split gate flash memory comprising:providing a plurality of memory cells wherein each memory cellcomprises: a select gate overlying a substrate and isolated from saidsubstrate by a select gate oxide layer; a first and second floating gateon opposite sidewalls of said select gate and isolated from said selectgate by an oxide spacer; and a control gate overlying said select gateand said first and second floating gates and isolated from said selectgate and said first and second floating gates by a dielectric layer; andproviding source and drain regions within said substrate and shared byadjacent said memory cells; wherein said first floating gate of a memorycell adjacent to said drain is to be programed, said programming methodcomprising: applying a positive select gate voltage to said select gateof said memory cell; applying a positive control gate voltage to saidcontrol gate of said memory cell; applying a positive drain voltage tosaid drain and connecting said source to ground; and connecting saidsubstrate to ground wherein hot electrons are injected from said sourceto said drain and into said first floating gate to program said firstfloating gate of said memory cell.
 21. A method of programming adual-bit split gate flash memory comprising: providing a plurality ofmemory cells wherein each memory cell comprises: a select gate overlyinga substrate and isolated from said substrate by a select gate oxidelayer; a first and second floating gate on opposite sidewalls of saidselect gate and isolated from said select gate by an oxide spacer; and acontrol gate overlying said select gate and said first and secondfloating gates and isolated from said select gate and said first andsecond floating gates by a dielectric layer; and providing source anddrain regions within said substrate and shared by adjacent said memorycells; wherein said second floating gate of a memory cell adjacent tosaid source is to be programed, said programming method comprising:applying a positive select gate voltage to said select gate of saidmemory cell; applying a positive control gate voltage to said controlgate of said memory cell; applying a positive source voltage to saidsource and connecting said drain to ground; and connecting saidsubstrate to ground wherein hot electrons are injected from said drainto said source and into said second floating gate to program said secondfloating gate of said memory cell.
 22. A method of erasing a dual-bitsplit gate flash memory comprising: providing a plurality of memorycells wherein each memory cell comprises: a select gate overlying asubstrate and isolated from said substrate by a select gate oxide layer;a first and second floating gate on opposite sidewalls of said selectgate and isolated from said select gate by an oxide spacer; and acontrol gate overlying said select gate and said first and secondfloating gates and isolated from said select gate and said first andsecond floating gates by a dielectric layer; and providing source anddrain regions within said substrate and shared by adjacent said memorycells; wherein said first floating gate of a memory cell adjacent tosaid drain is to be erased, said erasing method comprising: applying anegative control gate voltage to said control gate of said memory cell;applying a positive drain voltage to said drain and connecting saidsource to ground; and connecting said substrate to ground whereinelectrons are tunneled from said first floating gate into said drain toerase said first floating gate of said memory cell.
 23. A method oferasing a dual-bit split gate flash memory comprising: providing aplurality of memory cells wherein each memory cell comprises: a selectgate overlying a substrate and isolated from said substrate by a selectgate oxide layer; a first and second floating gate on opposite sidewallsof said select gate and isolated from said select gate by an oxidespacer; and a control gate overlying said select gate and said first andsecond floating gates and isolated from said select gate and said firstand second floating gates by a dielectric layer; and providing sourceand drain regions within said substrate and shared by adjacent saidmemory cells; wherein said second floating gate of a memory celladjacent to said source is to be erased, said erasing method comprising:applying a negative control gate voltage to said control gate of saidmemory cell; applying a positive source voltage to said source andconnecting said drain to ground; and connecting said substrate to groundwherein electrons are tunneled from said second floating gate into saidsource to erase said second floating gate of said memory cell.
 24. Amethod of reading a dual-bit split gate flash memory comprising:providing a plurality of memory cells wherein each memory cellcomprises: a select gate overlying a substrate and isolated from saidsubstrate by a select gate oxide layer; a first and second floating gateon opposite sidewalls of said select gate and isolated from said selectgate by an oxide spacer; and a control gate overlying said select gateand said first and second floating gates and isolated from said selectgate and said first and second floating gates by a dielectric layer; andproviding source and drain regions within said substrate and shared byadjacent said memory cells; wherein said first floating gate of a memorycell adjacent to said drain is to be read, said reading methodcomprising: applying a positive select gate voltage to said select gateof said memory cell; applying a positive control gate voltage to saidcontrol gate of said memory cell; applying a positive source voltage tosaid source; applying a zero drain voltage to said drain; and connectingsaid substrate to ground wherein a channel under said second floatinggate is forced into conductive depletion to read said first floatinggate of said memory cell.
 25. A method of reading a dual-bit split gateflash memory comprising: providing a plurality of memory cells whereineach memory cell comprises: a select gate overlying a substrate andisolated from said substrate by a select gate oxide layer; a first andsecond floating gate on opposite sidewalls of said select gate andisolated from said select gate by an oxide spacer; and a control gateoverlying said select gate and said first and second floating gates andisolated from said select gate and said first and second floating gatesby a dielectric layer; and providing source and drain regions withinsaid substrate and shared by adjacent said memory cells; wherein saidsecond floating gate of a memory cell adjacent to said source is to beread, said reading method comprising: applying a positive select gatevoltage to said select gate of said memory cell; applying a positivecontrol gate voltage to said control gate of said memory cell; applyinga positive drain voltage to said drain; applying a zero source voltageto said source; and connecting said substrate to ground wherein achannel under said first floating gate is forced into conductivedepletion to read said second floating gate of said memory cell.